A conventional window ball grid array (WBGA) semiconductor package uses a substrate having at least one through hole penetrating therethrough to allow a chip to be mounted on a surface of the substrate and over the through hole. A plurality of bonding wires go through the through hole and electrically connect the chip to the substrate. A plurality of solder balls are formed on a surface opposite to the chip-mounting surface of the substrate to electrically connect the chip to an external electronic device. This WBGA structure desirably shortens the bonding wires used for a central-pad type of chip, thereby reducing resistance of signal transmission and improving electrical performance and overall thickness of the semiconductor package.
The above conventional WBGA structure is shown in FIG. 5A, comprising a substrate 80 having an upper surface 81 and a lower surface 82, and a through hole 83 penetrating through the substrate 80. A plurality of conductive traces formed on the lower surface 82 of the substrate 80 are predefined with a plurality of wire-bonding regions 84 and ball-bonding regions 85. A chip 86 is mounted in a face down manner to allow its active surface 86a to be disposed on the upper surface 81 of the substrate 80 and over one end of the through hole 83, such that bond pads 87 of the chip 86 can be exposed via the through hole 83 and electrically connected to the corresponding wire-bonding regions 84 on the lower surface 82 of the substrate 80 by a plurality of bonding wires 88 going through the through hole 83. Then, a first encapsulation body 90 and a second encapsulation body 91 are respectively formed on the first surface 81 and the second surface 82 of the substrate 80, wherein the first encapsulation body 90 encapsulates the chip 86, and the second encapsulation body 91 is filled into the through hole 83 and encapsulates the bonding wires 88. Finally, a plurality of solder balls 92 are deposited on the ball-bonding regions 85 which are not encapsulated by the second encapsulation body 91, and the solder balls 92 serve as input/output (I/O) connections to electrically connect the chip 86 to an external printed circuit board (not shown). The relevant prior art references include U.S. Pat. Nos. 6,048,755, 6,190,943, 6,218,731, and 6,326,700, to name just a few, which relate to the WBGA package technology advantageously having more preferable electrical performance and compact size.
Besides the above mentioned benefits, however, the WBGA package undesirably renders a yield issue. In particular, for fabricating the first encapsulation body 90 and second encapsulation body 91, as shown in FIG. 5B, an encapsulation mold 95 having an upper mold 93 and a low mold 94 is used. The lower mold 94 is formed with a lower mold cavity 94a having a predetermined shape, unlike the one having a flat surface and used for a normal BGA package. During a molding or encapsulation process, the die-bonded and wire-bonded substrate 80 is placed in the encapsulation mold 95 and clamped between the upper and lower molds 93, 94. An epoxy resin material is injected into the encapsulation mold 95, wherein the epoxy resin is filled in an upper mold cavity 93a of the upper mold 93 to form the first encapsulation body 90 that encapsulates the chip 86, and filled in the lower mold cavity 94a of the lower mold 94 to form the second encapsulation body 91 that encapsulates the bonding wires 88. However, due to different sizes and clamping positions of the upper mold cavity 93a and lower mold cavity 94a, further as shown in FIG. 5B, non-clamping (NC) areas on the lower surface 82 of the substrate 80 are only supported by the lower mold 94 but not subject to a clamping force from the upper mold 93, such that the NC areas cannot be sufficiently and strongly clamped by the encapsulation mold 95 during molding, making the injected epoxy resin for fabricating the second encapsulation body 91 flash over the lower surface 82 of the substrate 80, as shown in FIGS. 5C and 5D (FIG. 5C is a cross-sectional view of FIG. 5D taken along the line 5C—5C). This resin flash f not only damages the surface planarity and external appearance of the semiconductor package, but also possibly contaminates the ball-bonding regions 85 predefined on the second surface 82 of the substrate 80, making the solder balls 92 fail to be perfectly bonded to the substrate 80 and thus adversely affecting the quality of electrical connection of the semiconductor package.
Therefore, the problem to be solved herein is to provide a WBGA semiconductor package which can eliminate the resin flash to thereby improve the quality of electrical connection and assure the surface planarity as well as provide a clean appearance for the semiconductor package.